Nature

Phase-Locked Loop Design in CMOS Technology

Phase-locked loops (PLLs) are indispensable timing and frequency synthesis circuits, finding application in communication transceivers, clock distribution, navigation receivers and sensor interfaces.
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 2)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
Nature

Phase-Locked Loop Techniques for Grid Synchronization in Power Systems

Phase-locked loops (PLLs) form the backbone of grid synchronisation in modern power systems. By aligning the phase and frequency of converter or inverter output with the mains voltage, PLLs ensure ...
EDN

Low Power Phase-Locked Loop with VCO

The 74HC/HCT4046A are phase-locked loop (PLL) with linear voltage-controlled oscillator (VCO) CMOS device having pins suited to 4046 in a 4000B series. These devices comply to JEDEC standard no. 7A.
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 1)

This is Part 1 of a three-part series. As modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher performance than ever before, they’re ...